1. Field of the Invention
The present invention generally relates to circuit design support systems, such as computer-aided design systems, and more specifically a circuit design system which designs a circuit on the basis of a functional specification thereof.
2. Description of the Related Art
Generally, it is required that a circuit, such as a large-scale integrated circuit, has a minimum number of gates and be produced at a minimum cost in a state in which the circuit has a time delay within a tolerable range and has an ability sufficient to drive a tolerable load. Generally, a circuit having a minimized scale has a larger number of logical stages, and hence longer delay times. A circuit capable of operating at a high speed has a large scale.
With the above in mind, a conventional circuit design method minimizes the scale of a desired circuit first, and performs, second, a timing check intended to determine whether or not a circuit having a minimized scale has delay times within a tolerable range. If a circuit portion having a delay time exceeding the tolerable range is identified, the circuit having the minimized scale is adjusted in order to reduce the delay time related to the above circuit portion.
Recent logic devices, such as computers and communications devices, have advanced functions and larger circuit scales. Under such circumstances, logic circuit design is becoming more complex. Hence, it is desired that a circuit design support system capable of efficiently designing desired circuits be provided.
FIG. 1 is a flowchart of a related circuit design method executed by a related circuit design support system. Functional specification data indicating logical expressions and truth tables, are applied to the system. In step S1, the system minimizes the logical sequences of a desired circuit. In step S2, the system assigns cells (circuit elements) to the respective minimized logical sequences.
When step S2 is completed, the desired circuit is automatically created.
In step S3, the system executes a load check and a load adjustment based on the load check. The load check is intended to check how many gates are connected to a gate. As shown in FIG. 2, where (n+1) gates G20-G2n (where n is an integer) are connected to a gate G1, there is no problem if the fan-out number of the gate G1 is equal to or larger than n+1. However, if the gate G1 has a fan-out number smaller than n+1, the gate G1 does not operate and load adjustment is needed.
The load adjustment is performed, as shown in FIG. 3. A buffer G3 is connected to the output terminal of the gate G1. The buffer G3 drives gates G20-G2i among the gates G20-G2n, and the gate G1 drives the remaining gates G2i+1-G2n. The gate G1 shown in FIG. 3 has a fan-out number within the specification.
In step S4, the system carries out a timing check. The timing check is intended to check whether or not the delay time of a gate including a signal line falls within a tolerable range. A signal transfer delay time Td between an input terminal i and output terminal x of a circuit element is approximately expressed as follows: EQU Td=Tix+C.multidot.K (1)
where Tix denotes a basic delay time between the input terminal i and output terminal x of the element, C denotes a load capacitance coupled to the output terminal x, and K denotes a delay time coefficient dependent on the load connected to the output terminal. The basic delay time Tix and the delay time coefficient are registered in a library unit provided in the circuit design support system.
The load capacitance C of the output terminal x is expressed as follows: EQU Cw=Cx+Ci (2)
where Cw denotes a net wiring line capacitance coupled to the output terminal x and proportional to the length of a wiring line, and Ci is the total input load capacitance of an input terminal of an element connected to the output terminal x.
Generally, where the circuit element being considered is a CMOS element, the term C.multidot.K, dependent on the load capacitance in the expression (1), is approximately equal to the basic delay time Tix when the circuit element being considered drives three to five input terminals of other elements connected to the output terminal x, although the term C.multidot.K depends on the types of the other elements. It can be seen from the above that the influence of the output load is great, as compared to the basic delay time Tix.
After the timing check in step S4, the system determines, in step S5, whether or not there is a timing error. The timing error means that the delay time Td defined in the expression (1) exceeds a rated delay time. If there is no timing error, the system ends the process shown in FIG. 1. If there is a timing error, the system executes, in step S6, a change process in which, for example, the number of logical stages is reduced to decrease the delay time Td. In step S7, the system determines whether or not there is an adjusted circuit portion. When the determination result is NO, the system ends the process. When the result of the determination in step S7 is YES, the system returns to step S2.
However, the related circuit design support process shown in FIG. 1 has a disadvantage in that the load check is executed in step S3 without taking into account the timing check, that is, time delays. In other words, the load check and timing check are separately carried out without taking each other into account. The related circuit design support process did not have a serious problem when circuits which do not have large scales are designed. However, recent computers and communications devices need circuits having very large scales. In this regard, a change in the logical structure, such as a reduction in the number of logical stages, needs an increased number of gates. With the above in mind, it is preferable that the logical structure be adjusted taking into the timing condition during the load check and adjustment process.